Publications

Found 12 results
Filters: Author is Eduardo Quinones  [Clear All Filters]
2016
L. Kosmidis, Quinones, E., Abella, J., Vardanega, T., Hernandez, C., Gianarro, A., Broster, I., and Cazorla, F. J., “Fitting Processor Architectures for Measurement-Based Probabilistic Timing Analysis”, 2016.
L. Kosmidis, Compagnin, D., Morales, D., Mezzetti, E., Quinones, E., Abella, J., Vardanega, T., and Cazorla, F. J., “Measurement-Based Timing Analysis of the AURIX Caches”. WCET 2016, 2016.
P. Benedicte, Kosmidis, L., Quinones, E., Abella, J., and Cazorla, F. J., “Modeling the Con dence of Timing Analysis for Time Randomised Caches”, SIES 2016, 2016.
P. Benedicte, Kosmidis, L., Quinones, E., Abella, J., and Cazorla, F. J., “Modeling the Confidence of Timing Analysis for Software Time Randomised Caches”, INDIN 2016, 2016.
M. Slijepcevic, Fernandez, M., Hernandez, C., Abella, J., Quinones, E., and Cazorla, F. J., “pTNoC: Time-Analyzable Scalable NoC Designs for Mixed-Criticality Multicore Embedded Systems”, DSD 2016, 2016.
L. Kosmidis, Vargas, R., Morales, D., Quinones, E., Abella, J., and Cazorla, F. J., “TASA: Toolchain-Agnostic Software Randomisation for Safety-Critical Real-Time Systems”, ICCAD 2016, 2016.
2015
M. Panic, Abella, J., Quinones, E., Hernandez, C., Ungerer, T., and Cazorla, F. J., “Analyzing TDMA and Round-Robin with MBPTA”, DSD 2015, 2015.
S. Milutinovic, Abella, J., Hardy, D., Quinones, E., Puaut, I., and Cazorla, F. J., “Speeding up Static Probabilistic Timing Analysis”, in ARCS, 2015.
J. Abella, Hernandez, C., Quinones, E., Cazorla, F. J., Conmy, P. Ryan, Azkarate-askasua, M., Perez, J., Mezzetti, E., and Vardanega, T., “WCET Analysis Methods: Pitfalls and Challenges on their Trustworthiness”, SIES 2015, 2015.
2014
G. Fernandez, Abella, J., Quinones, E., Rochange, C., Vardanega, T., and Cazorla, F. J., “Contention in multicore hardware shared resources: Understanding of the state of the art”. WCET 2014 workshop, 2014.
L. K. (BSC), Quinones, E., Abella, J., Vardanega, T., Broster, I., and Cazorla, F. J., “Probabilistic Timing Analysis and Its Impact on Processor Architecture”, 2014.
M. S. (BSC), (BSC), L. K., Abella, J., Quinones, E., and Cazorla, F., “Timing Verification of Fault-Tolerant Chips for Safety-Critical Applications in Harsh Environments”, in Special Issue on Harsh Chips, 2014.