Jaume Abella is a senior PhD. Researcher in the CAOS group at BSC and member of HIPEAC. He worked at the Intel Barcelona Research Center from 2005 to 2009 in the low-level design and modelling of circuits and microarchitectures for fault-tolerance and low power, and led the group on memory hierarchies. Jaume authored 15 patents at Intel.

He joined the BSC in 2009 where he is in charge of hardware designs for FP7 PROARTIS, BSC certification activities in VeTeSS, and involved in two ESA projects. He has authored more than 40 papers in top conferences and journals in the area. He is co-advisor of five PhD students.