Publications

Found 21 results
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2016
L. Kosmidis, Quinones, E., Abella, J., Vardanega, T., Hernandez, C., Gianarro, A., Broster, I., and Cazorla, F. J., “Fitting Processor Architectures for Measurement-Based Probabilistic Timing Analysis”, 2016.
L. Kosmidis, Compagnin, D., Morales, D., Mezzetti, E., Quinones, E., Abella, J., Vardanega, T., and Cazorla, F. J., “Measurement-Based Timing Analysis of the AURIX Caches”. WCET 2016, 2016.
P. Benedicte, Kosmidis, L., Quinones, E., Abella, J., and Cazorla, F. J., “Modeling the Con dence of Timing Analysis for Time Randomised Caches”, SIES 2016, 2016.
P. Benedicte, Kosmidis, L., Quinones, E., Abella, J., and Cazorla, F. J., “Modeling the Confidence of Timing Analysis for Software Time Randomised Caches”, INDIN 2016, 2016.
M. Slijepcevic, Fernandez, M., Hernandez, C., Abella, J., Quinones, E., and Cazorla, F. J., “pTNoC: Time-Analyzable Scalable NoC Designs for Mixed-Criticality Multicore Embedded Systems”, DSD 2016, 2016.
L. Kosmidis, Vargas, R., Morales, D., Quinones, E., Abella, J., and Cazorla, F. J., “TASA: Toolchain-Agnostic Software Randomisation for Safety-Critical Real-Time Systems”, ICCAD 2016, 2016.
2015
M. Panic, Abella, J., Quinones, E., Hernandez, C., Ungerer, T., and Cazorla, F. J., “Analyzing TDMA and Round-Robin with MBPTA”, DSD 2015, 2015.
S. Milutinovic, Quinones, E., Abella, J., and Cazorla, F. J., “PACO: Fast Average-Performance Estimation for Time-Randomized Caches”, 52nd Design Automation Conference (DAC), 2015.
E. Mezzetti, Ziccardi, M., Vardanega, T., Abella, J., Quinones, E., and Cazorla, F. J., “Randomized Caches Can Be Pretty Useful to Hard Real-Time Systems”. Leibniz Transactions on Embedded Systems (LITES), 2015.
S. Milutinovic, Abella, J., Hardy, D., Quinones, E., Puaut, I., and Cazorla, F. J., “Speeding up Static Probabilistic Timing Analysis”, in ARCS, 2015.
F. Wartel, Kosmidis, L., Gogonel, A., Baldovin, A., Stephenson, Z., Triquet, B., Quinones, E., Lo, C., Mezzetti, E., Broster, I., Abella, J., Cucu-Grosjean, L., Vardanega, T., and Cazorla, F. J., “Timing Analysis of an Avionics Case Study on Complex Hardware/Software Platforms”, in DATE, 2015.
J. Abella, Hernandez, C., Quinones, E., Cazorla, F. J., Conmy, P. Ryan, Azkarate-askasua, M., Perez, J., Mezzetti, E., and Vardanega, T., “WCET Analysis Methods: Pitfalls and Challenges on their Trustworthiness”, SIES 2015, 2015.
2014
J. Javier, Kosmidis, L., Abella, J., Quinones, E., and Cazorla, F. J., “Bus Designs for Time-Probabilistic Multicore Processors”, in Proceedings Design, Automation and Test in Europe, Dresden, Germany, 2014.
J. Abella, Hardy, D., Puaut, I., Quinones, E., and Cazorla, F. J., “On the Comparison of Deterministic and Probabilistic WCET Estimation Techniques”, in Proceedings 26th Euromicro Conference on Real-Time Systems (ECRTS14), 2014.
L. Kosmidis, Abella, J., Quinone, E., Wartel, F., Farrall, G., and Cazorla, F. J., “Containing Timing-Related Certification Cost in Automotive Systems Deploying Complex Hardware”, in Proceedings 51st Design Automation Conference (DAC), California, 2014.
G. Fernandez, Abella, J., Quinones, E., Rochange, C., Vardanega, T., and Cazorla, F. J., “Contention in multicore hardware shared resources: Understanding of the state of the art”. WCET 2014 workshop, 2014.
J. Abella, Quinones, E., Wartel, F., Vardanega, T., and Cazorla, F. J., “Heart of Gold: Making the Improbable Happen to Extend Coverage in Probabilistic Timing Analysis”, in Proceedings 26th Euromicro Conference on Real-Time Systems (ECRTS14), 2014.
L. K. (BSC), Quinones, E., Abella, J., Vardanega, T., Broster, I., and Cazorla, F. J., “Probabilistic Timing Analysis and Its Impact on Processor Architecture”, 2014.
L. Kosmidis, Abella, J., Wartel, F., Quinones, E., Colin, A., and Cazorla, F. J., “PUB: Path Upper-Bounding for Measurement-Based Probabilistic Timing Analysis”, in Proceedings 26th Euromicro Conference on Real-Time Systems (ECRTS14), 2014.
M. Slijepcevic, Kosmidis, L., Abella, J., Quiñones, E., and Cazorla, F. J., “Time-Analysable Non-Partitioned Shared Caches for Real-Time Multicore Systems”, in Proceedings 51st Design Automation Conference San Francisco DAC 2014 , California, 2014.
M. S. (BSC), (BSC), L. K., Abella, J., Quinones, E., and Cazorla, F., “Timing Verification of Fault-Tolerant Chips for Safety-Critical Applications in Harsh Environments”, in Special Issue on Harsh Chips, 2014.