Publications

Found 49 results
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2014
B. Lesage, Griffin, D., Davis, R., and Altmeyer, S., “On the application of Static Probabilistic Timing Analysis to Memory Hierarchies”. RTSOPS 2014, 2014.
J. Javier, Kosmidis, L., Abella, J., Quinones, E., and Cazorla, F. J., “Bus Designs for Time-Probabilistic Multicore Processors”, in Proceedings Design, Automation and Test in Europe, Dresden, Germany, 2014.
J. Abella, Hardy, D., Puaut, I., Quinones, E., and Cazorla, F. J., “On the Comparison of Deterministic and Probabilistic WCET Estimation Techniques”, in Proceedings 26th Euromicro Conference on Real-Time Systems (ECRTS14), 2014.
L. Kosmidis, Abella, J., Quinone, E., Wartel, F., Farrall, G., and Cazorla, F. J., “Containing Timing-Related Certification Cost in Automotive Systems Deploying Complex Hardware”, in Proceedings 51st Design Automation Conference (DAC), California, 2014.
G. Fernandez, Abella, J., Quinones, E., Rochange, C., Vardanega, T., and Cazorla, F. J., “Contention in multicore hardware shared resources: Understanding of the state of the art”. WCET 2014 workshop, 2014.
S. Altmeyer and Davis, R., “On the Correctness, Optimality and Precision of Static Probabilistic Timing Analysis”, in Proceedings Design, Automation and Test in Europe, Dresden, 2014.
J. Abella, Quinones, E., Wartel, F., Vardanega, T., and Cazorla, F. J., “Heart of Gold: Making the Improbable Happen to Extend Coverage in Probabilistic Timing Analysis”, in Proceedings 26th Euromicro Conference on Real-Time Systems (ECRTS14), 2014.
L. K. (BSC), Quinones, E., Abella, J., Vardanega, T., Broster, I., and Cazorla, F. J., “Probabilistic Timing Analysis and Its Impact on Processor Architecture”, 2014.
S. Altmeyer, Cucu-Grosjean, L., Davis, R. I., and Lesage, B., “Progress on static probabilistic timing analysis for systems with random cache replacement policies”. RTSOPS 2014, 2014.
L. Kosmidis, Abella, J., Wartel, F., Quinones, E., Colin, A., and Cazorla, F. J., “PUB: Path Upper-Bounding for Measurement-Based Probabilistic Timing Analysis”, in Proceedings 26th Euromicro Conference on Real-Time Systems (ECRTS14), 2014.
M. Slijepcevic, Kosmidis, L., Abella, J., Quiñones, E., and Cazorla, F. J., “Time-Analysable Non-Partitioned Shared Caches for Real-Time Multicore Systems”, in Proceedings 51st Design Automation Conference San Francisco DAC 2014 , California, 2014.
M. S. (BSC), (BSC), L. K., Abella, J., Quinones, E., and Cazorla, F., “Timing Verification of Fault-Tolerant Chips for Safety-Critical Applications in Harsh Environments”, in Special Issue on Harsh Chips, 2014.
2015
M. Panic, Abella, J., Quinones, E., Hernandez, C., Ungerer, T., and Cazorla, F. J., “Analyzing TDMA and Round-Robin with MBPTA”, DSD 2015, 2015.
M. Ziccardi, Mezzetti, E., Vardanega, T., Abella, J., and Cazorla, F. J., “EPC: Extended Path Coverage for Measurement-based Probabilistic Timing Analysis”, RTSS 2015, 2015.
J. Abella, del Castillo, J., Cazorla, F. J., and Padilla, M., “Extreme value theory in computer sciences: The case of embedded safety-critical systems”. 6th International Conference on Risk Analysis (ICRA), 2015.
I. Agirre, Azkarate-askasua, M., Perez, J., Hernandez, C., Abella, J., Vardanega, T., and Cazorla, F. J., “IEC-61508 SIL3-compliant Pseudo-Random Number Generators for Probabilistic Timing Analysis”, DSD 2015, 2015.
I. Agirre, Azkarate-askasua, M., Perez, J., Hernandez, C., Abella, J., Vardanega, T., and Cazorla, F. J., “IEC-61508 SIL3-compliant Pseudo-Random Number Generators for Probabilistic Timing Analysis”, DSD 2015, 2015.
I. Agirre, Azkarate-askasua, M., Perez, J., Hernandez, C., Abella, J., Vardanega, T., and Cazorla, F. J., “IEC-61508 SIL3-compliant Pseudo-Random Number Generators for Probabilistic Timing Analysis”, DSD 2015, 2015.
P. Ryan Conmy, Pearce, M., Ziccardi, M., Mezzetti, E., Vardanega, T., Anderson, J., Gianarro, A., Hernandez, C., and Cazorla, F. J., “Measurement-Based Probabilistic Timing Analysis: From Academia to Space Industry”, DASIA 2015, 2015.
S. Milutinovic, Quinones, E., Abella, J., and Cazorla, F. J., “PACO: Fast Average-Performance Estimation for Time-Randomized Caches”, 52nd Design Automation Conference (DAC), 2015.
C. Hernandez, Abella, J., Gianarro, A., Andersson, J., and Cazorla, F. J., “Random Modulo: a New Processor Cache Design for Safety-critical Systems”, DAC 2016, 2015.
C. Hernandez, Abella, J., Gianarro, A., Andersson, J., and Cazorla, F. J., “Random Modulo: a New Processor Cache Design for Safety-critical Systems”, DAC 2016, 2015.
E. Mezzetti, Ziccardi, M., Vardanega, T., Abella, J., Quinones, E., and Cazorla, F. J., “Randomized Caches Can Be Pretty Useful to Hard Real-Time Systems”. Leibniz Transactions on Embedded Systems (LITES), 2015.
I. Agirre, Azkarate-askasua, M., Larrucea, A., Perez, J., Vardanega, T., and Cazorla, F. J., “A safety concept for a railway mixed-criticality embedded system based on multicore partitioning”, DASC 2015, 2015.
I. Agirre, Azkarate-askasua, M., Larrucea, A., Perez, J., Vardanega, T., and Cazorla, F. J., “A safety concept for a railway mixed-criticality embedded system based on multicore partitioning”, DASC 2015, 2015.

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