L. K. (BSC), Quinones, E., Abella, J., Vardanega, T., Broster, I., and Cazorla, F. J., “Probabilistic Timing Analysis and Its Impact on Processor Architecture”, 2014.

S. Altmeyer, Cucu-Grosjean, L., Davis, R. I., and Lesage, B., “Progress on static probabilistic timing analysis for systems with random cache replacement policies”. RTSOPS 2014, 2014.

F. J. Cazorla, Abella, J., Anderson, J., Vardanega, T., Vatrinet, F., Bate, I., Broster, I., Azkarate-askasua, M., Wartel, F., Cucu, L., Cros, F., Farrall, G., Gogonel, A., Gianarro, A., Triquet, B., and Hernand, C., “PROXIMA: Improving Measurement-Based Timing Analysis through Randomisation and Probabilistic Analysis”, DSD 2016, 2016.

F. J. Cazorla, Abella, J., Anderson, J., Vardanega, T., Vatrinet, F., Bate, I., Broster, I., Azkarate-askasua, M., Wartel, F., Cucu, L., Cros, F., Farrall, G., Gogonel, A., Gianarro, A., Triquet, B., and Hernand, C., “PROXIMA: Improving Measurement-Based Timing Analysis through Randomisation and Probabilistic Analysis”, DSD 2016, 2016.

F. J. Cazorla, Abella, J., Anderson, J., Vardanega, T., Vatrinet, F., Bate, I., Broster, I., Azkarate-askasua, M., Wartel, F., Cucu, L., Cros, F., Farrall, G., Gogonel, A., Gianarro, A., Triquet, B., and Hernand, C., “PROXIMA: Improving Measurement-Based Timing Analysis through Randomisation and Probabilistic Analysis”, DSD 2016, 2016.

M. Slijepcevic, Fernandez, M., Hernandez, C., Abella, J., Quinones, E., and Cazorla, F. J., “pTNoC: Time-Analyzable Scalable NoC Designs for Mixed-Criticality Multicore Embedded Systems”, DSD 2016, 2016.

L. Kosmidis, Abella, J., Wartel, F., Quinones, E., Colin, A., and Cazorla, F. J., “PUB: Path Upper-Bounding for Measurement-Based Probabilistic Timing Analysis”, in Proceedings 26th Euromicro Conference on Real-Time Systems (ECRTS14), 2014.

C. Hernandez, Abella, J., Gianarro, A., Andersson, J., and Cazorla, F. J., “Random Modulo: a New Processor Cache Design for Safety-critical Systems”, DAC 2016, 2015.

C. Hernandez, Abella, J., Gianarro, A., Andersson, J., and Cazorla, F. J., “Random Modulo: a New Processor Cache Design for Safety-critical Systems”, DAC 2016, 2015.

E. Mezzetti, Ziccardi, M., Vardanega, T., Abella, J., Quinones, E., and Cazorla, F. J., “Randomized Caches Can Be Pretty Useful to Hard Real-Time Systems”. Leibniz Transactions on Embedded Systems (LITES), 2015.

D. Trilla, Hernandez, C., Abella, J., and Cazorla, F. J., “Resilient Random Modulo Cache Memories for Probabilistically-Analyzable Real-Time Systems”, IOLTS 2016, 2016.

I. Agirre, Azkarate-askasua, M., Larrucea, A., Perez, J., Vardanega, T., and Cazorla, F. J., “A safety concept for a railway mixed-criticality embedded system based on multicore partitioning”, DASC 2015, 2015.

I. Agirre, Azkarate-askasua, M., Larrucea, A., Perez, J., Vardanega, T., and Cazorla, F. J., “A safety concept for a railway mixed-criticality embedded system based on multicore partitioning”, DASC 2015, 2015.

S. Milutinovic, Abella, J., Hardy, D., Quinones, E., Puaut, I., and Cazorla, F. J., “Speeding up Static Probabilistic Timing Analysis”, in ARCS, 2015.

B. Lesage, Griffin, D., Altmeyer, S., and Davis, R. I., “Static Probabilistic Timing Analysis for Multi-path Programs”. In proceedings 36th Real-Time Systems Symposium (RTSS 2015), 2015.

S. Altmeyer, Cucu-Grosjean, L., and Davis, R., “Static probabilistic timing analysis for real-time systems using random replacement caches”, Real-Time Systems, vol. 51, pp. 77-123, 2015.

L. Kosmidis, Vargas, R., Morales, D., Quinones, E., Abella, J., and Cazorla, F. J., “TASA: Toolchain-Agnostic Software Randomisation for Safety-Critical Real-Time Systems”, ICCAD 2016, 2016.

M. Slijepcevic, Kosmidis, L., Abella, J., Quiñones, E., and Cazorla, F. J., “Time-Analysable Non-Partitioned Shared Caches for Real-Time Multicore Systems”, in Proceedings 51st Design Automation Conference San Francisco DAC 2014 , California, 2014.

F. Wartel, Kosmidis, L., Gogonel, A., Baldovin, A., Stephenson, Z., Triquet, B., Quinones, E., Lo, C., Mezzetti, E., Broster, I., Abella, J., Cucu-Grosjean, L., Vardanega, T., and Cazorla, F. J., “Timing Analysis of an Avionics Case Study on Complex Hardware/Software Platforms”, in DATE, 2015.

M. S. (BSC), (BSC), L. K., Abella, J., Quinones, E., and Cazorla, F., “Timing Verification of Fault-Tolerant Chips for Safety-Critical Applications in Harsh Environments”, in Special Issue on Harsh Chips, 2014.

C. Hernandez, Abella, J., Cazorla, F. J., Andersson, J., and Gianarro, A., “Towards Making a LEON3 Multicore Compatible with Probabilistic Timing Analysis”, DASIA 2015, 2015.

C. Hernandez, Abella, J., Cazorla, F. J., Andersson, J., and Gianarro, A., “Towards Making a LEON3 Multicore Compatible with Probabilistic Timing Analysis”, DASIA 2015, 2015.

J. Abella, Hernandez, C., Quinones, E., Cazorla, F. J., Conmy, P. Ryan, Azkarate-askasua, M., Perez, J., Mezzetti, E., and Vardanega, T., “WCET Analysis Methods: Pitfalls and Challenges on their Trustworthiness”, SIES 2015, 2015.

J. Abella, Hernandez, C., Quinones, E., Cazorla, F. J., Conmy, P. Ryan, Azkarate-askasua, M., Perez, J., Mezzetti, E., and Vardanega, T., “WCET Analysis Methods: Pitfalls and Challenges on their Trustworthiness”, SIES 2015, 2015.